Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

IO constraints for buses routed through FPGA

Hi, I hope this is the right place for this question... I have the following situation... * multiple SPI buses connected to my FPGA (connecting SPI slaves to FPGA) * a DSP a...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

For a pure combinational design, only the propagation delay matters, but for the overall operation, a sum of FPGA and slave delays (particularly for the most critical CLK to MISO delay) counts.