Intrroducing delay at pin level

Hello All,

I am new to the Quartus tool, I just need your help to solve my doubts.

I wanted to that "How to introduce output delay at pin level"

Example: I have two input signals inp1, inp2 and two output signal op1 , op2

op1 <= not inp1;

op2 <= not inp2;

So if you see both outputs behaves same way., because the are implemented using not gate..

Now I need let say 10 ns more delay at op2 compare to op1 on the real hard ware..

So achieve this what kind of constraints I have to give.

Thanks in advance

Pavan M