Intrroducing delay at pin level

Rather than being academic, I threw down a design with 4pins. I made the fast path have a max delay of 8ns. The delayed path had a min delay of 18ns and a max delay of 30ns.

Quartus did an excellent job routing the signal back and forth across the EPC3 device, giving us a cumulative delay on a single route of 25ns, so at the max timing model, it barely met that 30ns setup requirement. That being said, it still missed the min by a few nanoseconds. So I got rid of the max_delay requirement and reran, and it met timing. So the fitter did a quite impressive job.

Of course, I'm mixing timing models in this simplistic methodology, which isn't accurate. I'd really want to make one of the pins look like a clock, so I can relate the other path to it. Or just make sure the delay is greater than 10ns by visually comparing at the two timing models.