Introducing delay in output pin

Dear Rysc,

Thank you very much for your efforts in writing the 2 articles.

My case is different in 2 ways.

1. The constraints we apply will drive Quartus to adjust the clock delay (in PLL) to meet setup/hold at the external register. Firstly, in my design there is one clock which has to align with 3 different data lines (each of which have different board trace lengths). The clock can be adjusted to match with just one data line. What can I do for the other 2?

2. Secondly, I have one more constraint that the clock can vary from 3 MHz to 480 MHz based on user selection. If I use PLL for adjusting the delays, I need to specify the correct clock frequency, which is not possible in my case. In other words, I can't use PLL.

Can you please suggest a way out.

thanks and regards,

rajesh