Introducing delay in output pin

Technically, entering IO timing constraints that reflect your board requirements, and then result in delay being added, is the best way to go. I believe the fitter can even pull the register from the IO cell and put it in the fabric to increase the delay. But the biggest benefit of this is if the delay isn't added for whatever reason, you will see a timing failure.

That being said, IO constraints can be a pain. I've always done this through the Assignment Editor. I don't have CIV up in front of me, but something like Output Delay Chain 1 to the pin.

Then look in the Fitter Report's Delay Chain Summary to verify.