interrupts between processor and FPGA - cyclone v soc

Question

i want to exchange short interrupt driven messages between processors and between processors to the FPGA. 
how can I do it ? 
in xilinx zync ultra scale they have IPI mechanism (inter-processor interupt). is there any equivalent mechanism in cyclone v soc?

best regards,
ofer

eberlazare_i_intel · Answer

Hi,
Unfortunately, we do not have a design example for Cyclone V SoC, but you may refer below design example of the interrupts that uses Arria 10 SoC:
https://rocketboards.org/foswiki/Documentation/FPGASoftIPToLinuxApplicationExample2

Forum Discussion

interrupts between processor and FPGA - cyclone v soc

1 Reply

Recent Discussions

how to reduce clock skew between synchronous clock

Quartus 13.1 including Signal Tap License

I do not get an eMail with the generated license file

Installer cannot establish connection with SSL error

Quartus 20.1std compilation fails for Quartus map - Device 10AS057K2F40I1SG