Interpretation of numberic constants as signed/unsigned

anything in the ieee library (apart from std_logic_arith and std_logic_(un)signed) are part of the VHDL language specification, so you could term as "built in". It is just they need to be included when you write code. Integer and bit types are defined the in package std.standard which is included in every VHDL file by default.

Just to ensure you get the terminology correct, unsigned/signed dont overload any arithmetic operators, because they do no exist for any type. The "+", "-" etc are defined in the numeric_std library. Function overloading happens when you define a function with either different inputs or a more locally scoped version of the function - eg. you define a "+" function yourself that overloads the one you included from numeric_std (I would highly recommend you DONT do this).

You are correct about std_logic_vector - it is meant to represent a bus of bits. Keep this style in you head. There will be many many examples out there that use the std_logic_(un)signed libraries that treat std_logic_vector as the type included by the library, because these libraries were created by synopsys before the '93 revision of VHDL that included numeric_std. They became adopted by all of the vendors (and some had different implementation to others!) and were compiled into the IEEE library, which makes people think they are part of the VHDL spec.

They are safe to use now, but bare in mind that they are not part of the VHDL standard - you should be using numeric_std instead.