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Altera_Forum
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10 years ago

Interpretation of numberic constants as signed/unsigned

Hi All, I'm new to this forum, and very new to FPGAs. I've got myself a simple Cyclone II dev board and a copy of Quartus, and I'm attempting to learn some VHDL. I've just got to the stage of blin...
Altera_Forum's avatar
Altera_Forum
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10 years ago

the unsigned type is similar to the std_logic_vector type, in that it is an array of the std_logic type, but it is treated as an unsigned integer (there is also the signed type). Although it is very distinct from integer, as you cannot access individual bits from the integer type.

The type and subtype declarattions are functionally equivolent, because the subtype IS an integer type. It's not a type itself, it's a subtype.