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Altera_Forum's avatar
Altera_Forum
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13 years ago

Internally connect exported bus.

Hello. I want to split my qsys design into 2 parts: the A is Nios processor and some peripherials, and B is dsp. They both have to use sdram so the plan is to connect it in the top level system throu...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

Can you show a screenshot of your subsystems?

In the A subsystem, you should add a pipeline bridge, and connect the Nios' instruction and data masters to the pipeline bridge slave input. If you have DMAs that also need access to the SDRAM, connect them too to the pipeline bridge slave. Then on the pipeline bridge, define the master interface as an export.

Do the same thing on the subsystem B.

Then when you add both subsystems to the top level QSys design, both should appear with an Avalon master interface, and you can connect both to the SDRAM.