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Altera_Forum
Honored Contributor
Honored ContributorInternal Error: Sub-system: QIS File ....
I was attempting to synthesize a mixed VHDL Verilog design. This design compiles in older quartus versions (12 and 15.1), modelsim, and all xilinx tools, but it will not compile in Quartus Prime Pro ...
Altera_ForumHonored Contributor
Honored ContributorI submitted a service request, and they said they are searching their internal database.
