Interfacing Controller for SDR SDRAM Memory with FPGA Centric Approach

When you change the phase-shift of the PLL, you can change the setup and hold requirements, and the place-and-route will change to try and meet timing. So when changing the phase-shift, don't assume the place-and-route of everything else will be the same.

- When you do an 81 degree phase-shift, the -phase should be applied to the pll_clock, since that's where it is actually changing. You should be getting a PLL mismatch warning, stating that you're PLL timing constraints are different than the actual PLL is configured in hardware. This is bad. I recommend using derive_pll_clocks, since this will modify the PLL timing constraints whenever you change the PLL megafunction, so the constraints always match the hardware.

If you're modifying the PLL output to a phase-shift of 81 degrees, this affects both the data and clock going off-chip, and the shift basically cancels out, i.e. it's not buying you anything.

- I assume this is not DDR, just SDR(single-data rate). If so, you want to do a 180 degree phase-shift on the clock so that it is in the middle of the data window. This can be done in two ways: 1) Add another tap to the PLL that is 180 degrees phase-shifted and have that drive out H_sdram. 2) Just invert the clock going out H_sdram, and on that generated clock add -invert. In the end, you will have a setup relationship of 10ns and hold relationship of -10ns, and it should easily meet your timing requirements. (Should the -min value be -1 on your set_output_delay? If the Th requirement of the external device is 1ns, that becomes a -1ns for the -min value).

- On the input side, are the clock and data coming in edge aligned(i.e. they change at the same time) or center-aligned? I'm not sure from the description.