Interfaces and Synthesis

I am trying to use interfaces for use in abstraction and simplification of port connections. Something structs cannot do very well because they cannot carry information about direction. However, I cannot quite understand how an 'interface' interfaces to a top level file's ports.

Here is an example of some code I was testing with to try understanding interfaces.

// Interface definition
interface EMIF_Bus;
   input    logic   EMIF_addr;
   output   logic   EMIF_data;
   input    logic  EMIF_readEnable;
endinterface
// Top level 
module interface_top (
   input    clk,
   input    reset,
   EMIF_Bus chip_io
);
// Instantiating lower module
interface_sv SYSTEMVERILOG_DUT
(
   .clk        (clk),
   .reset      (reset),
   .module_io  (chip_io)
);

The following is an example of a dummy top level file for a quartus project. The submodule will assign an appropriate output depending upon address and read, but the important part is that this is synthesize without errors and through the technology map viewer I can verify it would function. The issue I did not expect is the dozens of warnings for permanently forcing tristate buffers as inputs or outputs. My understanding is that the declaration of "input" or "output" in the interface should remove the underlying notion of "inout" that is default for an signal that would not have a direction. However, the warnings would indicate that these port connections are being treated as "inout" rather than simply output or input.

Therefore, I am trying to clarify my misunderstanding of interfaces.