Interfaces and Synthesis

Looking back on the sources I have used on this topic I misunderstood and botched the syntax. It should have looked like this.

interface EMIF_Bus (
      input    wire   EMIF_addr,
      output   logic   EMIF_data,
      input    wire  EMIF_readEnable
   );
endinterface
module interface_top (
   input    clk,
   input    reset,
   input        addr,
   output       data,
   input    readEnable
);
EMIF_Bus module_io (
   .EMIF_addr        (addr),
   .EMIF_data        (data),
   .EMIF_readEnable  (readEnable)
);
interface_sv SYSTEMVERILOG_DUT
(
   .clk        (clk),
   .reset      (reset),
   .module_io  (module_io)
);

The above interface definition allows for external variables and nets to be connected to the interface. However, it requires a declaration and connection of external variables/nets to the interface. From there any module sharing this declared interface will have access to these signals. So, this solves the issue.