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Altera_Forum's avatar
Altera_Forum
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15 years ago

Interface for external RAM and LPM RAM

I switched to Quartus 9.0 from 6.1. I used "Interface to User Logic" for external RAM(MRAM) and LPM RAM. Instead of them, I added new components in SOPC Builder. Is there any problem in VHDL ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

In your vhdl code, the connection between data and dat is unidirectional, which is probably not what you intended.

But why are you using vhdl in the first place? Can't you define your external RAM as a tristate slave and just declare all the signals that you need?