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Altera_Forum's avatar
Altera_Forum
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15 years ago

Interface for external RAM and LPM RAM

I switched to Quartus 9.0 from 6.1.

I used "Interface to User Logic" for external RAM(MRAM) and LPM RAM.

Instead of them, I added new components in SOPC Builder.

Is there any problem in VHDL discription?

library IEEE;

use IEEE.std_logic_1164.all;

use IEEE.numeric_std.all;

entity MRAM is

port (

address : in std_logic_vector(17 downto 0) ; --avalon_tristate_slave.address

data : inout std_logic_vector(15 downto 0) ; -- .data

byteenable_n : in std_logic_vector(1 downto 0) ; -- .byteenable_n

chipselect_n : in std_logic ; -- .chipselect_n

read_n : in std_logic ; -- .read_n

write_n : in std_logic ; -- .write_n

add : out std_logic_vector(17 downto 0); -- conduit_end.export

dat : inout std_logic_vector(15 downto 0) ;

be_n : out std_logic_vector(1 downto 0);

cs_n : out std_logic ;

oe_n : out std_logic ;

we_n : out std_logic

);

end entity MRAM;

architecture rtl of MRAM is

begin

add <= address;

be_n <= byteenable_n;

cs_n <= chipselect_n;

oe_n <= read_n;

we_n <= write_n;

dat <= data;

end architecture rtl; -- of MRAM

Thanks

2 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    15 years ago

    In your vhdl code, the connection between data and dat is unidirectional, which is probably not what you intended.

    But why are you using vhdl in the first place? Can't you define your external RAM as a tristate slave and just declare all the signals that you need?
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    15 years ago

    Thanks for reply.

    I had a problem that only data port was export when I created a tristate slave.

    showthread.php?p=88948 (I can't post links)

    So I had to write HDL code but the problem was resolved just now.

    It was mainly with my own circuit. VHDL code is here.

    -- MRAM.vhd

    library IEEE;

    use IEEE.std_logic_1164.all;

    use IEEE.numeric_std.all;

    entity MRAM is

    port (

    data : inout std_logic_vector(15 downto 0) := (others => '0'); -- avalon_tristate_slave.data

    byteenable_n : in std_logic_vector(1 downto 0) := (others => '0'); -- .byteenable_n

    chipselect_n : in std_logic := '0'; -- .chipselect_n

    read_n : in std_logic := '0'; -- .read_n

    write_n : in std_logic := '0'; -- .write_n

    address : in std_logic_vector(17 downto 0) := (others => '0'); -- .address

    add : out std_logic_vector(17 downto 0); -- conduit_end.export

    be_n : out std_logic_vector(1 downto 0); -- .export

    cs_n : out std_logic; -- .export

    oe_n : out std_logic; -- .export

    wr_n : out std_logic -- .export

    );

    end entity MRAM;

    architecture rtl of MRAM is

    begin

    add <= address;

    be_n <= byteenable_n;

    cs_n <= chipselect_n;

    oe_n <= read_n;

    wr_n <= write_n;

    end architecture rtl; -- of MRAM