Intel RGMII example - output delay failure

Hi,

Shifting the latch clock does not help in this case - This refers to the path in the design without PLL.

"Take an example of the path in the design without PLL, the amount of setup slack is smaller than the amount of the hold violation. Shifting the latch clock does not help in this case."

From the report, there is setup slack of 3.839ns and hold slack of -4.917ns for the path mentioned above as an example. Setup slack of 3.839ns means the signal arrives at a time of 3.839ns earlier than what is required. Hold slack of -4.917ns means the current signal has to stay for another 4.917ns longer before the next signals comes in. If the new signal arrives the destination after another 4.917ns, the signal will fail the setup because the setup slack has only 3.839ns.

I have to understand this...

We have data incoming to our system and driving input DDR flip flops.

We have a clock that's connect to the wrong pin - so it's a mile away from the DDR flip flops. Indeed a problem !

BUT with a PLL - we shift the clock such that its edges are perfectly center aligned to the data.

Why center aligning the clock to the data (with a PLL) doesn't solve our problem ?

Are you saying that for some reason we won't be able to shift the clock correctly ?

Or are you saying that having the clock driving the DDR flip flop perfectly center aligned isn't enough in this case ?

In the design you have attached, there is hold violation for some paths. The data arrival time is less than the data required time. From the screenshot above, you can see that the data required time improves a little (-0.648ns) but this is not enough. After adding the PLL, the data required time is reduced by this amount but it is still larger than the data arrival time. If you change the pin location to increase the data arrival time, you will see positive hold slack.

Thanks

Best regards,

KhaiY