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New Contributor
5 years agoIntel PCIE 512bit Controller
Hi,
I am using Intel P tile avalon MM PCIe Express and Intel PCIE 512 bit controller
Warning(16735): Verilog HDL warning at intel_pcie_dma_hwtcl.sv(329): actual bit length 174 differs from formal bit length 160 for port "desc_rdata_o"
Warning(16735): Verilog HDL warning at inigo_pcie_intel_pcie_dma_0.v(64): actual bit length 32 differs from formal bit length 174 for port "dma_wrdm_tx_data_i"
I am getting these kind of warning while synthesis
mainly its because of IP parameterization of PCIe DMA
here VFNUM address width
PFNUM address width
STATUS_DATA_WIDTH
STATUS_DATA_WIDHT
how can i fill these columns ?
anyone please explain with example
Thanks