Intel HLS streaming problem

Hi @MUsman​

sorry for the late response.

The problem was indeed on my end. What I didn’t see was that the fifo accepted10 identical values and gave them back correctly to the test bench. Like you said, it’s as designed.

Our problem was with the way we used the fifo. We used the sopc fifo generator instead of directly using the dc_fifo megafunction inside our VHDL. With the sopc version, the only way to see if a fifo is empty is by using the avalon interfaces. This was injecting huge delay in our design. Our hardware module was able to read multiple erroneous value before receiving the empty signal from the fifo. Using the dc_fifo and its empty signal fixed everything.

Thanks & regards