Intel HLS streaming problem

Hi @EGaut​ ,

I have looked into the testbench and HLS component.

This is not a bug,

Refer to zoomed out version of Waveform. Testbench provide 10 valid inputs on the read stream (both valid and ready are high as per the avalon spec). The component then reads from the specified address in memory and provides 10 valid writes with the correct data from memory on the output stream (both valid and ready are high as per the avalon spec)

Further I modified your testbench to mimic same scenario, with gap between read/ write.

Read valid is high for one clock cycle, you can see correct behavior.

Attached a waveform for ref

for further reading you may want to refer to avalon spec

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/manual/mnl_avalon_spec.pdf

PAGE 47

Hopefully this will address the question.

Thanks,

Arslan