Intel HLS 17.1 verilog code generation error.

I do not know what you did, that it works well.

But with me it works the same way.

// Generated by Intel(R) HLS Compiler, Version 18.1.0 Build 625

/////////////////////////////////////////////////////////////////

// MODULE hls_aes256_internal

/////////////////////////////////////////////////////////////////

module hls_aes256_internal

(

input logic clock,

input logic resetn,

input logic clock2x,

output logic done_irq,

// AVS avs_control

input logic avs_control_enable,

input logic avs_control_read,

input logic avs_control_write,

input logic avs_control_address,

input logic [7:0] avs_control_writedata,

input logic avs_control_byteenable,

output logic [7:0] avs_control_readdata,

output logic avs_control_readdatavalid,

// AVS avs_cra

input logic avs_cra_enable,

input logic avs_cra_read,

input logic avs_cra_write,

input logic [1:0] avs_cra_address,

input logic [63:0] avs_cra_writedata,

input logic [7:0] avs_cra_byteenable,

output logic [63:0] avs_cra_readdata,

output logic avs_cra_readdatavalid,

// AVS avs_in_data

input logic avs_in_data_enable,

input logic avs_in_data_read,

input logic avs_in_data_write,

input logic avs_in_data_address,

input logic [127:0] avs_in_data_writedata,

input logic [15:0] avs_in_data_byteenable,

output logic [127:0] avs_in_data_readdata,

output logic avs_in_data_readdatavalid,

// AVS avs_key

input logic avs_key_enable,

input logic avs_key_read,

input logic avs_key_write,

input logic [2:0] avs_key_address,

input logic [31:0] avs_key_writedata,

input logic [3:0] avs_key_byteenable,

output logic [31:0] avs_key_readdata,

output logic avs_key_readdatavalid,

// AVS avs_out_data

input logic avs_out_data_enable,

input logic avs_out_data_read,

input logic avs_out_data_write,

input logic [2:0] avs_out_data_address,

input logic [15:0] avs_out_data_writedata,

input logic [1:0] avs_out_data_byteenable,

output logic [15:0] avs_out_data_readdata,

output logic avs_out_data_readdatavalid

);