Intel HLS 17.1 verilog code generation error.

Hi @LKwia​

Indeed what you quoted as HLS output is incorrect.

I have tried to create a similar component on my HLS 18.1 Standard Edition Windows 10, I got the correct output (dsee code snippets below).

My suggestion to you will be to update to latest version.

C++ Component Definition:

component void hls_aes256(
	hls_avalon_slave_memory_argument(1) uint8_t *control,
	hls_avalon_slave_memory_argument(32) uint8_t *key,
	hls_avalon_slave_memory_argument(16) uint8_t *in_data,
	hls_avalon_slave_memory_argument(16) uint8_t *out_data,
	 int N
	) 

Verilog Output:

// Generated by Intel(R) HLS Compiler, Version 18.1.0 Build 625
 
/////////////////////////////////////////////////////////////////
// MODULE hls_aes256_internal
/////////////////////////////////////////////////////////////////
 
module hls_aes256_internal
(
   input logic clock,
   input logic resetn,
   input logic [31:0] N,
   input logic start,
   output logic busy,
   output logic done,
   input logic stall,
   // AVS avs_control
   input logic avs_control_enable,
   input logic avs_control_read,
   input logic avs_control_write,
   input logic avs_control_address,
   input logic [7:0] avs_control_writedata,
   input logic avs_control_byteenable,
   output logic [7:0] avs_control_readdata,
   output logic avs_control_readdatavalid,
   // AVS avs_in_data
   input logic avs_in_data_enable,
   input logic avs_in_data_read,
   input logic avs_in_data_write,
   input logic [3:0] avs_in_data_address,
   input logic [7:0] avs_in_data_writedata,
   input logic avs_in_data_byteenable,
   output logic [7:0] avs_in_data_readdata,
   output logic avs_in_data_readdatavalid,
   // AVS avs_key
   input logic avs_key_enable,
   input logic avs_key_read,
   input logic avs_key_write,
   input logic [4:0] avs_key_address,
   input logic [7:0] avs_key_writedata,
   input logic avs_key_byteenable,
   output logic [7:0] avs_key_readdata,
   output logic avs_key_readdatavalid,
   // AVS avs_out_data
   input logic avs_out_data_enable,
   input logic avs_out_data_read,
   input logic avs_out_data_write,
   input logic [3:0] avs_out_data_address,
   input logic [7:0] avs_out_data_writedata,
   input logic avs_out_data_byteenable,
   output logic [7:0] avs_out_data_readdata,
   output logic avs_out_data_readdatavalid
);

Thanks,

Arslan