Intel HLS 17.1 verilog code generation error.

I cannot comment on your HLS problem but the OpenCL compilation is not working because of this error:

C:/Users/user/Desktop/OpenCL_AES/aes256/system/synthesis/submodules/acl_fifo_stall_valid_lookahead.sv Line: 25

Error (10759): Verilog HDL error at aes256_system.v(311): object aes256Encrypt_finish declared in a list of port declarations cannot be redeclared within the module body File: C:/Users/user/Desktop/OpenCL_AES/aes256/system/synthesis/submodules/aes256_system.v Line: 311

Are you using an HDL library in the OpenCL code? I don't see why you would get such error with a standard OpenCL design.