Intel HLS 17.1 verilog code generation error.

@LKwia​

Hi,

I am looking at this thread, I am not sure if I understand you correctly.

Are you asking why HLS generate Verilog code ? or is there any problem in generated code ? Please specify.

HLS is intended to generate the HDL code (Verilog) in this case, that can be used later in Quartus to generate programming file or to integrate with rest of your design.

You might want to take a look at our HLS web page.

https://www.intel.com/content/www/us/en/software/programmable/quartus-prime/hls-compiler.html

Thanks,

Arslan