New ContributorIntel FPGA Unique Chip ID always zero
Hi,
I added the Unique Chip ID Intel FPGA IP to my platform for an Arria V FPGA.
To read the Chip ID I created a custom IP with a Avalon Streaming Sink (data[63:0],valid) and split the data into two 32-bit registers to read the ID directly with 2x 32 Bit-PIO-Ports. The PIO ports are used to access the Chip ID via Nios II soft processor.
Problem:
Although "valid" is '1' which is supposed to signal a ready Chip ID the value is always 0. See below attached Signal Tap Screenshot.
For some reason it is not possible to trigger neither on falling edge of 'reset' nor on rising edge of 'data_valid'.
Note:
System with Nios II Processor is running, so there must be a working reset and clock.
Thanks for your help.
Cheers, Sven
The problem occured due to an improper reset wich is active high for the Unique Chip ID IP. Furthermore, the timing of the reset pulse seemed to be relevant in some way.
Solution:
I apply a delayed reset pulse to the reset input of the Unique Chip ID IP which is a bit longer than the asked 10 clock cycles.
