Forum Discussion
swtsven
New Contributor
New ContributorIntel FPGA Unique Chip ID always zero
Hi,
I added the Unique Chip ID Intel FPGA IP to my platform for an Arria V FPGA.
To read the Chip ID I created a custom IP with a Avalon Streaming Sink (data[63:0],valid) and split the data into ...
The problem occured due to an improper reset wich is active high for the Unique Chip ID IP. Furthermore, the timing of the reset pulse seemed to be relevant in some way.
Solution:
I apply a delayed reset pulse to the reset input of the Unique Chip ID IP which is a bit longer than the asked 10 clock cycles.
EricMunYew_C_Intel
Frequent Contributor
Frequent ContributorCan you try to read the chip_id[63:0] directly after your FPGA is fully loaded and when data_valid is high.
