Integrating HDL module with Altera OpenCL BSP

I am currently trying to integrate my custom HDL into the OpenCL BSP. I am using a bittware s5_net board. I found that even a simple pass through hdl code does not work. I added some pass through logic (avalon ST single clock fifo) to the "system.qsys" file and added channels to board_spec.xml. The opencl code simply writes to the pass through logic and reads from it.

channel uint inChannel __attribute__((io("rtl_in")));

channel uint outChannel __attribute__((io("rtl_out")));

# define DATA_SIZE 100

__kernel void write_to_rtl(__global uint *restrict input_data)

{

int offset = 0;

int data = 0;

for(offset = 0; offset < DATA_SIZE; offset++)

{

data = input_data[offset];

write_channel_altera(outChannel, data);

}

}

__kernel void read_from_rtl(__global uint *restrict output_data)

{

int offset = 0;

int data = 0;

for(offset = 0; offset < DATA_SIZE; offset++)

{

data = read_channel_altera(inChannel);

output_data[offset] = data;

}

}

Do I need to add anything else ? I would really appreciate any suggestions on this. I have been trying to debug it for the past few days, trying out various combinations. I did not find anything suspicious in the generated qsys files, although trying to read the autogenerated opencl hdl did not help much.

However, if I just replace my io channels with an opencl channel, it works find. Thus I know that the rest of the code works.

I have attached the generated qsys files, the updated board_spec.xml and my opencl code.

Any suggestions on this would really helpful.

Thanks

Nilim