Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
18 years ago

Instantiation Components Compile error

Hi, I'm new to Quartus 6.1 Web Edition software. I bought the CYCLONE FPGA Starter Board and tries to learn how to use Quartus 6.1 that came with the board. The problem I'm having is with ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
17 years ago

Yes, the present unreasonable construct wouldn't be possible in a Verilog always @ (posedge C) block.

Unfortunately, I don't know what's the intended behaviour, under which conditions the action A <= '0'; shall be peformed. A possible synthesizable variant would be this: 

if C'EVENT AND C='1' then
  if  V='0' then
    A <= '1';
  else
    A <= '0';
  end if;
end if;