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Altera_Forum's avatar
Altera_Forum
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18 years ago

Instantiation Components Compile error

Hi, I'm new to Quartus 6.1 Web Edition software. I bought the CYCLONE FPGA Starter Board and tries to learn how to use Quartus 6.1 that came with the board. The problem I'm having is with ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
17 years ago

Try this, it works.

:)

-----------------------------------------

LIBRARY ieee;

USE ieee.std_logic_1164.all;

USE ieee.numeric_std.all;

ENTITY compt IS

PORT (

C, V :IN std_logic;

A :OUT std_logic);

END ENTITY compt;

ARCHITECTURE arc OF compt IS

begin

process(C)

begin

if (C'EVENT AND C='1' AND V='0') then

A <= '1';

else

A <= '0';

end if;

end process;

end arc;

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