Instantiation Components Compile error

Hi,

I'm new on VHDL and QUARTUS II. I receive errors from compilation because of 'ELSE' in my code. I don't understand why Quartus II don't recognize ELSE, WAIT FOR , and WHEN . Please help me, I want know.

This is one of my code which don't compile successfuly :

LIBRARY ieee;

USE ieee.std_logic_1164.all;

USE ieee.numeric_std.all;

---------------------------

ENTITY compt IS

PORT (

C: IN STD_LOGIC;

V: IN STD_LOGIC;

A: OUT STD_LOGIC

);

END compt;

---------------------------

ARCHITECTURE arc OF compt IS

BEGIN

IF (C'EVENT AND C='1' AND V='0') THEN

A <= '1';

ELSE

A <= '0';

END IF;

END arc;

Error (10500): VHDL syntax error at compt.vhd(21) near text "IF"; expecting "end", or "(", or an identifier ("if" is a reserved keyword), or a concurrent statement

Error (10500): VHDL syntax error at compt.vhd(21) near text "THEN"; expecting "<="

Error (10500): VHDL syntax error at compt.vhd(23) near text "ELSE"; expecting "end", or "(", or an identifier ("else" is a reserved keyword), or a concurrent statement

Error (10500): VHDL syntax error at compt.vhd(25) near text "IF"; expecting ";", or an identifier ("if" is a reserved keyword), or "architecture"

Really thank you by advance

Pascale