Honored Contributor
Honored ContributorHi endian,
Here's the message I get from the processing tab. It did find the right numbers of entity-architecture in the parts_lib.vhd file, and a total of 14 design units which I assume to be the 7 design units in the parts_lib.vhd file + the number of design units of the comp_pkg.vhd file, although not clearly stated in the processing tab. Again, it stop compiling at the first component unit which the compiler states being used but not declared as if the comp_pkg.vhd file is not being seen by the compiler although I've included it with files. One think that worth to be mentioned. The working directory is one that I've created on a different folder named D:\projects\vhdl\Full_Adder\ and the top level file and the two others (parts_lib.vhd and the comp_pkg.vhd) are in the same directory. Again, thanks for your help. Info: ******************************************************************* Info: Running Quartus II Analysis & Synthesis Info: Version 6.1 Build 201 11/27/2006 SJ Web Edition Info: Processing started: Tue Jun 26 17:15:41 2007 Info: Command: quartus_map --read_settings_files=on --write_settings_files=off full_adder -c full_adder Info: Found 1 design units, including 0 entities, in source file comp_pkg.vhd Info: Found design unit 1: comp_pkg Info: Found 14 design units, including 7 entities, in source file parts_lib.vhd Info: Found design unit 1: and_2-and_2_arch Info: Found design unit 2: and_3-and_3_arch Info: Found design unit 3: nand_2-nand_2_arch Info: Found design unit 4: nand_3-nand_3_arch Info: Found design unit 5: or_2-or_2_arch Info: Found design unit 6: xor_2-xor_2_arch Info: Found design unit 7: xor_3-xor_3_arch Info: Found entity 1: and_2 Info: Found entity 2: and_3 Info: Found entity 3: nand_2 Info: Found entity 4: nand_3 Info: Found entity 5: or_2 Info: Found entity 6: xor_2 Info: Found entity 7: xor_3 Info: Found 2 design units, including 1 entities, in source file full_adder.vhd Info: Found design unit 1: full_adder-full_adder_arch Info: Found entity 1: full_adder Error (10482): VHDL error at full_adder.vhd(19): object "xor_3" is used but not declared Error: Quartus II Analysis & Synthesis was unsuccessful. 1 error, 0 warnings Info: Allocated 129 megabytes of memory during processing Error: Processing ended: Tue Jun 26 17:15:43 2007 Error: Elapsed time: 00:00:02 Error: Quartus II Full Compilation was unsuccessful. 1 error, 0 warnings
