Instanciating dual port memory with different r/w widths

Here is an example that builds horribly wrong. I expected Table to be split into any kind of memory even without the ramstyle attrib, but fails. It all goes into ALUT's (stratix III, Q10.1sp1 and Q11.0sp1).

 
--testing the record to mem instanciation
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all; 
use ieee.std_logic_arith.all; 
entity record_mem is
port
(
    --write bus
    clk1    : in std_logic;
    de1     : in std_logic;
    adr1    : in std_logic_vector(8 downto 0);
    data1   : in std_logic_vector(31 downto 0);
    --32bit output from the record array
    clk2    : in std_logic;
    adr2    : in std_logic_vector(7 downto 0);
    data2   : out std_logic_vector(31 downto 0);
    --16bit output from the record array
    clk3    : in std_logic;
    adr3    : in std_logic_vector(7 downto 0);
    data3   : out std_logic_vector(15 downto 0);
    --8bit output from the record array
    clk4    : in std_logic;
    adr4    : in std_logic_vector(8 downto 0);
    data4   : out std_logic_vector(7 downto 0)
);
end record_mem;
architecture rtl of record_mem is
    type TableEntry is record
        record_32bit_at_adr0                        : std_logic_vector(31 downto 0);
        record_16bit_at_adr1_high_word              : std_logic_vector(15 downto 0);
        record_8bit_at_adr1_low_word_low_byte       : std_logic_vector(7 downto 0);
        record_8bit_at_adr1_low_word_high_byte      : std_logic_vector(7 downto 0);
    end record;
    type TableArray is array (integer range 255 downto 0) of TableEntry;
    signal Table : TableArray;
    alias adr1_wordadr   : std_logic_vector(0 downto 0) is adr1(0 downto 0);
    alias adr1_memidx    : std_logic_vector(7 downto 0) is adr1(adr1'high downto 1);
    alias adr4_wordadr   : std_logic_vector(0 downto 0) is adr4(0 downto 0);
    alias adr4_memidx    : std_logic_vector(7 downto 0) is adr4(adr4'high downto 1);
begin
    write_dp_mem:process (clk1)
    begin
        if(rising_edge(clk1)) then
            if(de1='1') then
                case conv_integer(adr1_wordadr) is
                when 0=>
                    Table(conv_integer(adr1_memidx)).record_32bit_at_adr0    <=data1;
                when 1=>
                    Table(conv_integer(adr1_memidx)).record_16bit_at_adr1_high_word            <=data1(31 downto 16);
                    Table(conv_integer(adr1_memidx)).record_8bit_at_adr1_low_word_low_byte     <=data1(7 downto 0);
                    Table(conv_integer(adr1_memidx)).record_8bit_at_adr1_low_word_high_byte    <=data1(15 downto 8);
                when others=>
                end case;
            end if;
        end if;
    end process;
    read_32bit_mem:process (clk2)
    begin
        if(rising_edge(clk2)) then
            data2<=Table(conv_integer(adr2)).record_32bit_at_adr0;
        end if;
    end process;
    read_16bit_mem:process (clk3)
    begin
        if(rising_edge(clk3)) then
            data3<=Table(conv_integer(adr3)).record_16bit_at_adr1_high_word;
        end if;
    end process;
    read_8bit_mem:process (clk4)
    begin
        if(rising_edge(clk4)) then
            if(conv_integer(adr4_wordadr)=0) then
                data4<=Table(conv_integer(adr4_memidx)).record_8bit_at_adr1_low_word_low_byte;
            else
                data4<=Table(conv_integer(adr4_memidx)).record_8bit_at_adr1_low_word_high_byte;
            end if;
        end if;
    end process;
end rtl;