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Altera_Forum
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11 years ago

Input wants to be assigned and constrained as Clock

Hi, I'm running mad with this: I've got tree inputs of asynchronous Signals. These Signals are the ABZ-Signals of a device which meassures a movement (I just don't know how it is called in en...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
11 years ago

Hmmm, Code, you want code. OK here is all I can give you:

https://www.alteraforum.com/forum/attachment.php?attachmentid=8595

As I see it NOW:

The three wires which are leading down from the ABZ-Wires, goto some counters, which are counting the POSITIVE EDGES of the Signals.

MEA CULPA

This is why Quartus thinks these are clocks.

OK, in this case I have to change the counters to sample the Inputs and counting a change in a 2Bit shift-register.

Sometimes speaking about a Problem helps also to solve the Problem.

Thanks