Input wants to be assigned and constrained as Clock

Some ideas:

- Look for messages in synthesis about latches being inferred. It's hard to mistakenly create a register, but easy to create latches.

- Change your file to SystemVerilog and use the always_ff, always_comb structures. (I'm not sure what synthesis does if make a mistake, and not certain it errors out, but conceptually I like these constructs, especially when getting started)

- Launch TimeQuest and type "derive_clocks -period 10.0". This puts a 10ns clock constraint on everything that TQ thinks is a clock. (Note that you should never do this in a real design, but this is for a test). Then run Report Clocks in the task to see which clocks are created. I assume these will show up as clocks. If they do, run:

report_timing -setup -to_clock <insert_clk_name_here> -detail full_path -panel_name "to clock"

report_timing -setup -from_clock <insert_clk_name_here> -detail full_path -panel_name "from clock"

This should show paths with registers driven by that clock.

- Go to the RTL view and trace forward from that signal to all the destinations. There should be a register or latch showing up.