Input Signals in ModelSim

Hi, I've started yesterday with ModelSim. Since I'm learning it my own and don't know who to ask, I'm posting this probably stupid question to you (sorry).

I saw when I have input signals to my verilog module, in ModelSim I'll have to explicitely set them, even to 0, alternatively they stay undefined. I read that I always should set not just the clock, but also a reset signal happening after certain period of time in the beginning. Now, I need a "start" impulse happening, and I noticed simply setting "start" to high after a certain time, leaves it high forever. So, I'm currently setting it then later to low. I'm trying to model here a 50 MHz clock.

Currently I'm doing it e.g. like this in transcript:

force -deposit /reset 0 0, 1 50 ns, 0 100 ns
force -deposit clk 1 0, 0 {10 ns} -repeat 20 ns
force /start 0 0, 1 100 ns, 0 200 ns

The module declaration looks as follows..

module algo(
    input clk,
    input start,
    input reset,
    output reg  leds,
    input write,
    input  writedata,
    output reg  readdata,
    output done
);

Questions:

Am I doing this actually correctly?

In my Verilog design should I also try to set signals to low when they're handled, e.g. the "start"?

When giving e.g. the start impulse, for how long actually should I leave it high in ModelSim?