inout wire logic, quartus15.1, error

Using Quartus 15.1 I have the following issue,

when I'm using this construction

- inout wire logic [31:0] SIG1; - it is working correctly,

but when I define logic [31:0] in typedef into package and using import package, how

- package def_type;

typedef logic [31:0] SIG1_WIDTH_T;

endpackage

inout SIG1_WIDTH_T SIG1;

The Quartus send me an Error (10170): Verilog HDL syntax error..

The last one scheme is run correctly by Synplify & NCSIM, and Quartus 15.1 according it's Help supports Package & User-defined types