Inout pin Warning

I am using Quartus Prime Standard Edition

fx3_dq is directly connected to FPGA pins, but is also passed into a module like so:

fx3 fx3_inst(

.reset(reset)

,.clk(clk)

,.fdata(fx3_dq)

,.sloe(fx3_sloe_n)

.....

);

This is just an example and inside the module there is an assign like so for fdata:

assign fdata = (slwr_loopback_1d_) ? 8'dz : data_from_hps;

The code is the sample project from FX3; I'm not sure if I can post it but I have a link to the page.

http://www.cypress.com/documentation/application-notes/an65974-designing-ez-usb-fx3-slave-fifo-interface

On my top level do I also need a tri-state as mentioned? Or should the tri-state be taken care of with the assign statement in the module?

Thank you