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Altera_Forum
Honored Contributor
9 years ago?! someone can please help me with that issues -
I tried to change the signals and give more time delay such that data for reading and writing will be enough to take over. after trying to reading again the 28h and 29 h registers i get the results of 20h and 21h (for reading the registers respectively ) after number of clocks, but then the data bus goes to 01h value at finish. the signals from model-sim: