Honored Contributorwhat should i do?
"Info: Register "state[3][0]" lost all its fanouts during netlist optimizations." state is a variable of size 0 to 31 of std_logic_vector(7 downto 0). In modelsim, the vhdl code seem to work fine. Hope you can help me. Thanks.
Honored ContributorIt's likely that the signal state[3][0] does not drive any logic or to be more clear, no output of your design depends on this signal. Quartus will optimize it away. Hence no fan out.
See if you can follow that bit of the vector through and see if any output depend on it. Or Maybe there is another signal in your design that is an identical copy of state[3][0] and this was used by Quartus during netlist optimization in place of the state[3][0]. i.e Quartus will remove duplicate logic if it canHonored Contributoric, thanks for the info.
my design took a long time to synthesis, therefore i shorten the code to check whether part of the state variable can be read.
