Thanks everyone for helping me. I managed to solve the problem by adding clock to the module. Here's the final code :
module LUT256DFF (
Clk,
ADDR, // Address input
DataOut, // Data output
RE, // Read Enable
CE // Chip Enable
) /* synthesis romstyle = "M4K" */;
input Clk;
input ADDR;
output DataOut;
input RE,CE;
(* romstyle = "M4K" *) reg mem ;
reg DataOut;
always @ (posedge Clk)
begin
if (CE && RE)
DataOut <= mem;
end
initial begin
$readmemb("sine_value.list", mem); // sine_value is pre-calcualted external memory file
end
endmodule
It will synthesize to 2048bits of RAM (altsyncram). One question, is this RAM has the same attribute with the cyclone II's M4K ROM ?