Inferring RAM, registered on inputs only

Well for a start, "reset triggered initialisation process" is not possible on any ram inside any device. Try using a reset to get a value in a ram, and you'll only get logic.

Here's a sanitized version of code that can be inferred. Both options are incorrect for my purposes.# 1 is registered on the wrong side.# 2 has unintended read-new-data bypass logic

library ieee;
use ieee.std_logic_1164.all;
entity my_memory is
  generic(
    g_addr_bits : natural := 8;
    g_data_bits : natural := 8);
  port(   
    clk_i      : in  std_logic;
    r_en_i     : in  std_logic; 
    r_addr_i   : in  std_logic_vector(g_addr_bits-1 downto 0);
    r_data_o   : out std_logic_vector(g_data_bits-1 downto 0);
    w_en_i     : in  std_logic;
    w_addr_i   : in  std_logic_vector(g_addr_bits-1 downto 0);
    w_data_i   : in  std_logic_vector(g_data_bits-1 downto 0));
end my_memory;
architecture rtl of my_memory is
  type ram_t is array(2**g_addr_bits-1 downto 0) of
    std_logic_vector(g_data_bits-1 downto 0);
    
  signal ram : ram_t := ...; -- Magic initial value goes here
  signal r_addr : std_logic_vector(g_addr_bits-1 downto 0);
begin
  
  main : process(clk_i)
    begin
      if rising_edge(clk_i) then
        if w_en_i = '1' then
          ram(to_integer(unsigned(w_addr_i))) <= w_data_i;
        end if;
        -- Option# 1: reads old-data
        -- Registered on output (r_data_o), not input (r_addr_i)
        r_data_o <= ram(to_integer(unsigned(r_addr_i)));
        -- Option# 2: registered on input
        r_addr <= r_addr_i;
      end if;
    end process;
  
  -- Option# 2: no register on output, but implies reads new-data
  -- (reading new data requires costly bypass logic from quartus)
  r_data_o <= ram(to_integer(unsigned(r_addr)));
end rtl;

Here's a version that has the correct register behaviour (registered inputs and unregistered outputs) and the correct read-write behaviour (reads old data). Unfortunately, it is not possible to initialize it using a generic parameter.

library ieee;
use ieee.std_logic_1164.all;
library altera_mf;
use altera_mf.altera_mf_components.all;
entity my_memory is
  generic(
    g_addr_bits : natural := 8; 
    g_data_bits : natural := 8);
  port(
    clk_i      : in  std_logic;
    r_en_i     : in  std_logic;
    r_addr_i   : in  std_logic_vector(g_addr_bits-1 downto 0);
    r_data_o   : out std_logic_vector(g_data_bits-1 downto 0);
    w_en_i     : in  std_logic;
    w_addr_i   : in  std_logic_vector(g_addr_bits-1 downto 0); 
    w_data_i   : in  std_logic_vector(g_data_bits-1 downto 0));
end my_memory;
architecture rtl of my_memory is
begin
  altsyncram_component : altsyncram
    generic map (
      --intended_device_family => "Arria II GX",   
      address_aclr_b                     => "NONE",  
      address_reg_b                      => "CLOCK0",
      clock_enable_input_a               => "BYPASS",
      clock_enable_input_b               => "BYPASS",
      clock_enable_output_b              => "BYPASS",
      lpm_type                           => "altsyncram",  
      numwords_a                         => 2**g_addr_bits,
      numwords_b                         => 2**g_addr_bits,
      operation_mode                     => "DUAL_PORT",
      outdata_aclr_b                     => "NONE",
      outdata_reg_b                      => "UNREGISTERED",
      power_up_uninitialized             => "FALSE", 
      rdcontrol_reg_b                    => "CLOCK0",  
      read_during_write_mode_mixed_ports => "OLD_DATA",    
      widthad_a                          => g_addr_bits,
      widthad_b                          => g_addr_bits,
      width_a                            => g_data_bits,   
      width_b                            => g_data_bits,
      width_byteena_a                    => 1)
    port map (
      clock0    => clk_i, 
      wren_a    => w_en_i,  
      address_a => w_addr_i,
      data_a    => w_data_i,
      rden_b    => r_en_i,  
      address_b => r_addr_i, 
      q_b       => r_data_o);
end rtl;

The device families I am targeting are Aria 2 and 5. These have M9K and M10K blocks which support the behaviour I desire: read-old-data, registers inputs, unregistered outputs.

For the alt sync ram method, you can specify an initialisation file of a .mif or .hex via the generics.

I've solved this problem. For anyone who finds this via google:

have you tried with a shared variable instead of a signal, so see how it affects the read-before-write behaviour? it never used to make a difference, would be nice to see if Altera fixed it.