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Altera_Forum's avatar
Altera_Forum
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13 years ago

Inferring FIFO in VHDL

I'm trying to write a synchronous FIFO in VHDL, and I get the following message : Info (276007): RAM logic "sRAM" is uninferred due to asynchronous read logic I already asked google, and ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

The problem is i think in using the readptr as asynchronous address AND doing calculations on it. If you put the read statement inside the process it willl probalby infer (but with slightly different behaviour of course). Worth a try?