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Altera_Forum
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10 years ago

Inferred RAM: Pass-through logic generated despite no_rw_check

Dear all, I'm a hobbyist currently learning VHDL. My learning vehicle is a self-developed RISC-V CPU that that I develop in the Lite edition of Quartus Prime 15.1. The CPU is working fine alrea...
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Altera_Forum
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10 years ago

Where does your R0?

If you want to ensure reading always 0 , just create register with initialized value, and use keep attribute or preserve assignment. No operation write to register . or you can separate by AND-gate internal and external.

you can use one register near RAM to output on sclear or sload signals.

I don't know but RAM should have async clear for input/output register. will it be good solution?