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Altera_Forum
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10 years ago

Inferred RAM: Pass-through logic generated despite no_rw_check

Dear all, I'm a hobbyist currently learning VHDL. My learning vehicle is a self-developed RISC-V CPU that that I develop in the Lite edition of Quartus Prime 15.1. The CPU is working fine alrea...
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Altera_Forum
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10 years ago

This indeed makes perfect sense and also explains why my original code is synthesized in the observed fashion. Seems that the "read-during-write" problem as implied by the synthesizer warning is not about concurrent reads and writes at all in this case ;)