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Altera_Forum
Honored Contributor
Honored ContributorInferred RAM: Pass-through logic generated despite no_rw_check
Dear all, I'm a hobbyist currently learning VHDL. My learning vehicle is a self-developed RISC-V CPU that that I develop in the Lite edition of Quartus Prime 15.1. The CPU is working fine alrea...
Altera_ForumHonored Contributor
Honored Contributorwonderful.
you can put if statment outside case statement. look at changes. So find the structure that your await.
