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Altera_Forum
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10 years ago

Inferred RAM: Pass-through logic generated despite no_rw_check

Dear all, I'm a hobbyist currently learning VHDL. My learning vehicle is a self-developed RISC-V CPU that that I develop in the Lite edition of Quartus Prime 15.1. The CPU is working fine alrea...
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Altera_Forum
Icon for Honored Contributor rankHonored Contributor
10 years ago

wonderful.

you can put if statment outside case statement. look at changes. So find the structure that your await.