Altera_Forum
Honored Contributor
Honored ContributorInfering dual port ROM
Hello;
I'd like to get a VHDL code to infere a dual port ROM but with a registered address. ThanksForum Discussion
7 Replies
Altera_ForumIt always pays to Read the manual:
https://www.altera.com/content/dam/altera-www/global/en_us/pdfs/literature/hb/qts/qts_qii5v1.pdf section 12 (specially page 12-27 - Inferring ROM Functions from HDL Code)- Altera_Forum--- Quote Start --- It always pays to Read the manual: https://www.altera.com/content/dam/altera-www/global/en_us/pdfs/literature/hb/qts/qts_qii5v1.pdf section 12 (specially page 12-27 - Inferring ROM Functions from HDL Code) --- Quote End --- Thanks for your attention. I refereed to this section. But it has a registered output dual ROM. I want a registered address dual ROM.
- Altera_Forum
What exactly do you mean by "registered address" rom? All internal memory elements require a registered read address in order to infer the code into memory blocks, otherwise it will infer a LUTram.
- Altera_Forum
Thanks M.Tricky for ur attension.
I mean a "registered read address" dual ROM, Is there a VHDL code to infer it? - Altera_Forum
Why not just register the read address before reading from ROM?
It doesnt need a specific code example, just put together a register and a ROM. - Altera_Forum
OK;
These ROMs are part of pipeline, I tried to infer an asynchronous read address and read data ROM but I failed. It is ok if there is a code to infer a non registered read address or read data ROMs. - Altera_Forum
Asynchronous read address rams (ie. read address not registered) can only be inferred using LUTRAM.
