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Altera_Forum
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17 years ago

Incorrect behaviour of DSPBuilder 7.1SP1 block SinglePulse in hardware

Hello everyone, we dicovered an incorrect behaviour of the DSPBuilde block SinglePulse when we integrated it in a QuartusII design and brought it to our StratixII FPGA. Our environment is ...
Altera_Forum's avatar
Altera_Forum
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17 years ago

Sorry for my late reply, I was out of office the last days.

Attached to this post you can find a TestPulse.zip which includes the DSPBuilder model and all generated files ... (our environment is DSPBuilder 7.1SP1, QuartusII 7.1SP1, Matlab 2006b)

In order to test the generated code we opend the quartusII project that was created by DSPBuilder in the corresponding subfolder. We also attached SignalTapII logic to it within quartus, so the quartusII project was modified after it's gerneration with SignalCompiler.

I hope we can get an idea what is going wrong with this example design.

Thanks, Bernhard