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Altera_Forum
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17 years ago

Incorrect behaviour of DSPBuilder 7.1SP1 block SinglePulse in hardware

Hello everyone, we dicovered an incorrect behaviour of the DSPBuilde block SinglePulse when we integrated it in a QuartusII design and brought it to our StratixII FPGA. Our environment is ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
17 years ago

Could you post the very simple design you mentioned (just to be sure there's no misunderstanding)?