incomplete sensitivity list check in Quartus II

You have over specified on this process, as it is a synchronous process. You only need to add signals to the sensitivity list that can cause a change in the output values. For a synchronous process, values can only change when you get a clock edge - this causes the process to re-run.

Any signal in a sensitivity list will cause that process to be re-evaluated on signal change in simulation. So adding too many signals can cause simulations to slow down as it keeps re-evaluating the process unnecessarily. On the flip side, for a non-synchronous process, adding too few signals can cause simulation behaviour to missmatch the real logic. For example:

process(clk)
begin
  if clk = '1' then
    op <= ip1 and ip2;
  end if;
end process;

In simulation, the waveform for this process would make it look like a clocked process. But the synthesis tool would create a transparent latch. This would cause missmatches.