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Altera_Forum's avatar
Altera_Forum
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12 years ago

incomplete sensitivity list check in Quartus II

I wrote some VHDL code with incomplete sensitivity list as following and compile it with Quartus II. But, Quartus II didn't give any warnings on this. Does anybody know how to make quatus ii to ch...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
12 years ago

bertulus, thanks for your answer, what's the principle for adding signals to sensitivity list? For the code below, is the sensitivity list complete? 

   process (vin_clk,rst_n,frame_flag_vin,vin_de,data_cnt)
   begin
      if rising_edge(vin_clk) then
         if (rst_n = '0') then
            data_cnt <= (others=>'0');
         elsif (frame_flag_vin = '1') then
            data_cnt <= (others=>'0');
         elsif (vin_de = '1') then
            if (data_cnt = vin_width - 1) then
               data_cnt <= (others=>'0');
            else
               data_cnt <= data_cnt + 1;
            end if;
         else
            data_cnt <= data_cnt;
         end if;
      end if;
   end process;