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Hi Mohamed,
I haven't found any way to control the build via including .qsys directly, which is why I went with Tcl scripting.
Practically though, why do you care if its VHDL? So long as the design synthesizes, you shouldn't really need to care.
There are no manual steps with the Tcl script. The script automates everything.
In the case of the DDR controller, it also automates the application of the DDR pin constraints file generated by the IP core via a post-flow script. None of the Altera examples do this :)
Cheers,
Dave
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Hi Dave,
I was using SOPC builder previously and have just now learned how to use Qsys... So I came across your post where you mentioned "Practically though, why do you care if its VHDL? So long as the design synthesizes, you shouldn't really need to care."
I have a project consisting of several blocks in schematic interface, they are mainly custom blocks written in VHDL, what I want to do is, to include the Nios system in the schematic interface.
In SOPC, when I was trying to generate the Nios system, I will be prompted to select either Verilog or VHDL whenever I want to create a new Nios system, but I could not find this option in Qsys.
May I ask:
1. Is there a way to select either Verilog or VHDL to be generated in Qsys?
2. Does it matter? If no, could I still combine the Nios system generated in Verilog to communicate well with all the custom blocks written in VHDl where I am going to combine all of them in schematic file?
Thank you in advance for your guidance
Honored Contributor
